d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:160:9:@11ns:(report note): a
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:162:9:@11ns:(report note): Checks: 1
Passed: 1
Failed: 0
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:166:9:@11ns:(report note): b
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:168:9:@11ns:(report note): Checks: 1
Passed: 1
Failed: 0
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:172:9:@60ns:(report note): c
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:174:9:@60ns:(report note): Checks: 2
Passed: 1
Failed: 1
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:179:9:@61ns:(report note): d
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:181:9:@61ns:(report note): Checks: 2
Passed: 1
Failed: 1
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:185:9:@61ns:(report note): e
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:187:9:@61ns:(report note): Checks: 2
Passed: 1
Failed: 1
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:191:9:@80ns:(report note): f
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:193:9:@80ns:(report note): Checks: 3
Passed: 2
Failed: 1
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:198:9:@81ns:(report note): g
d:\Programming\github\vunit\vunit\vhdl\check\test\tb_check_sequence.vhd:200:9:@81ns:(report note): Checks: 3
Passed: 2
Failed: 1
d:\Programming\github\vunit\vunit\vhdl\check\test\test_support.vhd:297:5:@81ns:(report note): 
-----------
Test result
-----------
d:\Programming\github\vunit\vunit\vhdl\check\test\test_support.vhd:303:5:@81ns:(report note): Number of assertions: 2
d:\Programming\github\vunit\vunit\vhdl\check\test\test_support.vhd:304:5:@81ns:(report note): Number of errors: 0
simulation stopped @81ns with status 0
